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1 ビッ ト CDC CDC-1 クリティカル 1 ビッ ト CDC パスが、 同期化されていないか、 または不明の CDC 回路を含みます。
だそうだ。CE 制御の CDC CDC-15 警告 ク ロ ッ ク イネーブルで制御された CDC。
## add_wave /apatb_DMA_pow2_top/m_axi_gmem_BUSER -into $wdata_group -radix hex
ERROR: [Wavedata 42-471] Note: Nothing was found for the following items: /apatb_DMA_pow2_top/m_axi_gmem_BUSER
ERROR: [Common 17-39] 'add_wave' failed due to earlier errors.
while executing
"add_wave /apatb_DMA_pow2_top/m_axi_gmem_BUSER -into $wdata_group -radix hex"
(file "DMA_pow2.tcl" line 103)
// ==============================================================
// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2021.2 (64-bit)
// Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
// ==============================================================
`timescale 1ns/1ps
module DMA_pow2_control_s_axi
#(parameter
C_S_AXI_ADDR_WIDTH = 6,
C_S_AXI_DATA_WIDTH = 32
)(
input wire ACLK,
input wire ARESET,
input wire ACLK_EN,
input wire [C_S_AXI_ADDR_WIDTH-1:0] AWADDR,
input wire AWVALID,
output wire AWREADY,
input wire [C_S_AXI_DATA_WIDTH-1:0] WDATA,
input wire [C_S_AXI_DATA_WIDTH/8-1:0] WSTRB,
input wire WVALID,
output wire WREADY,
output wire [1:0] BRESP,
output wire BVALID,
input wire BREADY,
input wire [C_S_AXI_ADDR_WIDTH-1:0] ARADDR,
input wire ARVALID,
output wire ARREADY,
output wire [C_S_AXI_DATA_WIDTH-1:0] RDATA,
output wire [1:0] RRESP,
output wire RVALID,
input wire RREADY,
output wire interrupt,
input wire clk,
input wire rst,
output wire ap_start,
input wire ap_done,
input wire ap_ready,
input wire ap_idle,
input wire [31:0] ap_return,
output wire [63:0] in_r,
output wire [63:0] out_r,
input wire [0:0] ap_local_deadlock
);
//------------------------Address Info-------------------
// 0x00 : Control signals
// bit 0 - ap_start (Read/Write/COH)
// bit 1 - ap_done (Read/COR)
// bit 2 - ap_idle (Read)
// bit 3 - ap_ready (Read/COR)
// bit 7 - auto_restart (Read/Write)
// others - reserved
// 0x04 : Global Interrupt Enable Register
// bit 0 - Global Interrupt Enable (Read/Write)
// others - reserved
// 0x08 : IP Interrupt Enable Register (Read/Write)
// bit 0 - enable ap_done interrupt (Read/Write)
// bit 1 - enable ap_ready interrupt (Read/Write)
// bit 5 - enable ap_local_deadlock interrupt (Read/Write)
// others - reserved
// 0x0c : IP Interrupt Status Register (Read/TOW)
// bit 0 - ap_done (COR/TOW)
// bit 1 - ap_ready (COR/TOW)
// bit 5 - ap_local_deadlock (COR/TOW)
// others - reserved
// 0x10 : Data signal of ap_return
// bit 31~0 - ap_return[31:0] (Read)
// 0x18 : Data signal of in_r
// bit 31~0 - in_r[31:0] (Read/Write)
// 0x1c : Data signal of in_r
// bit 31~0 - in_r[63:32] (Read/Write)
// 0x20 : reserved
// 0x24 : Data signal of out_r
// bit 31~0 - out_r[31:0] (Read/Write)
// 0x28 : Data signal of out_r
// bit 31~0 - out_r[63:32] (Read/Write)
// 0x2c : reserved
// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
//------------------------Parameter----------------------
localparam
ADDR_AP_CTRL = 6'h00,
ADDR_GIE = 6'h04,
ADDR_IER = 6'h08,
ADDR_ISR = 6'h0c,
ADDR_AP_RETURN_0 = 6'h10,
ADDR_IN_R_DATA_0 = 6'h18,
ADDR_IN_R_DATA_1 = 6'h1c,
ADDR_IN_R_CTRL = 6'h20,
ADDR_OUT_R_DATA_0 = 6'h24,
ADDR_OUT_R_DATA_1 = 6'h28,
ADDR_OUT_R_CTRL = 6'h2c,
WRIDLE = 2'd0,
WRDATA = 2'd1,
WRRESP = 2'd2,
WRRESET = 2'd3,
RDIDLE = 2'd0,
RDDATA = 2'd1,
RDRESET = 2'd2,
ADDR_BITS = 6;
//------------------------Local signal-------------------
reg [1:0] wstate = WRRESET;
reg [1:0] wnext;
reg [ADDR_BITS-1:0] waddr;
wire [C_S_AXI_DATA_WIDTH-1:0] wmask;
wire aw_hs;
wire w_hs;
reg [1:0] rstate = RDRESET;
reg [1:0] rnext;
reg [C_S_AXI_DATA_WIDTH-1:0] rdata;
wire ar_hs;
wire [ADDR_BITS-1:0] raddr;
// internal registers
reg int_ap_idle;
reg int_ap_ready = 1'b0;
reg int_ap_done = 1'b0;
wire ap_done_get;
reg ap_done_ext;
reg int_ap_start = 1'b0;
wire ap_start_set;
reg ap_start_mask;
reg int_auto_restart = 1'b0;
wire auto_restart_set;
reg int_gie = 1'b0;
reg [5:0] int_ier = 6'b0;
wire ier_toggle;
reg ier_mask;
reg [5:0] int_isr = 6'b0;
wire isr_toggle;
reg isr_mask;
reg [31:0] int_ap_return;
reg [63:0] int_in_r = 'b0;
reg [63:0] int_out_r = 'b0;
//------------------------Instantiation------------------
//------------------------AXI write fsm------------------
assign AWREADY = (wstate == WRIDLE);
assign WREADY = (wstate == WRDATA);
assign BRESP = 2'b00; // OKAY
assign BVALID = (wstate == WRRESP);
assign wmask = { {8{WSTRB[3]}}, {8{WSTRB[2]}}, {8{WSTRB[1]}}, {8{WSTRB[0]}} };
assign aw_hs = AWVALID & AWREADY;
assign w_hs = WVALID & WREADY;
// wstate
always @(posedge ACLK) begin
if (ARESET)
wstate <= WRRESET;
else if (ACLK_EN)
wstate <= wnext;
end
// wnext
always @(*) begin
case (wstate)
WRIDLE:
if (AWVALID)
wnext = WRDATA;
else
wnext = WRIDLE;
WRDATA:
if (WVALID)
wnext = WRRESP;
else
wnext = WRDATA;
WRRESP:
if (BREADY)
wnext = WRIDLE;
else
wnext = WRRESP;
default:
wnext = WRIDLE;
endcase
end
// waddr
always @(posedge ACLK) begin
if (ACLK_EN) begin
if (aw_hs)
waddr <= AWADDR[ADDR_BITS-1:0];
end
end
//------------------------AXI read fsm-------------------
assign ARREADY = (rstate == RDIDLE);
assign RDATA = rdata;
assign RRESP = 2'b00; // OKAY
assign RVALID = (rstate == RDDATA);
assign ar_hs = ARVALID & ARREADY;
assign raddr = ARADDR[ADDR_BITS-1:0];
// rstate
always @(posedge ACLK) begin
if (ARESET)
rstate <= RDRESET;
else if (ACLK_EN)
rstate <= rnext;
end
// rnext
always @(*) begin
case (rstate)
RDIDLE:
if (ARVALID)
rnext = RDDATA;
else
rnext = RDIDLE;
RDDATA:
if (RREADY & RVALID)
rnext = RDIDLE;
else
rnext = RDDATA;
default:
rnext = RDIDLE;
endcase
end
// rdata
always @(posedge ACLK) begin
if (ACLK_EN) begin
if (ar_hs) begin
rdata <= 'b0;
case (raddr)
ADDR_AP_CTRL: begin
rdata[0] <= int_ap_start;
rdata[1] <= int_ap_done;
rdata[2] <= int_ap_idle;
rdata[3] <= int_ap_ready;
rdata[7] <= int_auto_restart;
end
ADDR_GIE: begin
rdata <= int_gie;
end
ADDR_IER: begin
rdata <= int_ier;
end
ADDR_ISR: begin
rdata <= int_isr;
end
ADDR_AP_RETURN_0: begin
rdata <= int_ap_return[31:0];
end
ADDR_IN_R_DATA_0: begin
rdata <= int_in_r[31:0];
end
ADDR_IN_R_DATA_1: begin
rdata <= int_in_r[63:32];
end
ADDR_OUT_R_DATA_0: begin
rdata <= int_out_r[31:0];
end
ADDR_OUT_R_DATA_1: begin
rdata <= int_out_r[63:32];
end
endcase
end
end
end
//------------------------Register logic-----------------
assign interrupt = int_gie & (|int_isr);
assign ap_start = int_ap_start;
assign ap_start_set = w_hs && waddr == ADDR_AP_CTRL && WSTRB[0] && WDATA[0];
assign ap_done_get = ar_hs && raddr == ADDR_AP_CTRL && int_ap_done;
assign auto_restart_set = w_hs && waddr == ADDR_AP_CTRL && WSTRB[0];
assign isr_toggle = w_hs && waddr == ADDR_ISR && WSTRB[0];
assign in_r = int_in_r;
assign out_r = int_out_r;
// ap_start_mask
always @(posedge clk) begin
if (rst)
ap_start_mask <= 1'b0;
else
ap_start_mask <= ap_start_set;
end
// int_ap_start
always @(posedge clk) begin
if (rst)
int_ap_start <= 1'b0;
else if (ap_start_set == 1'b1 && ap_start_mask == 1'b0)
int_ap_start <= 1'b1;
else if (ap_ready)
int_ap_start <= int_auto_restart; // clear on handshake/auto restart
end
// ap_done_ext
always @(posedge clk) begin
if (rst)
ap_done_ext <= 1'b0;
else
ap_done_ext <= ap_done_get;
end
// int_ap_done
always @(posedge clk) begin
if (rst)
int_ap_done <= 1'b0;
else if (ap_done)
int_ap_done <= 1'b1;
else if (ap_done_get == 1'b0 && ap_done_ext == 1'b1)
int_ap_done <= 1'b0; // clear on read
end
// int_ap_idle
always @(posedge clk) begin
if (rst)
int_ap_idle <= 1'b0;
else
int_ap_idle <= ap_idle;
end
// int_ap_ready
always @(posedge clk) begin
if (rst)
int_ap_ready <= 1'b0;
else
int_ap_ready <= ap_ready;
end
// int_auto_restart
always @(posedge clk) begin
if (rst)
int_auto_restart <= 1'b0;
else if (auto_restart_set == 1'b1)
int_auto_restart <= WDATA[7];
end
// int_gie
always @(posedge clk) begin
if (rst)
int_gie <= 1'b0;
else if (w_hs && waddr == ADDR_GIE && WSTRB[0])
int_gie <= WDATA[0];
end
// int_ier
always @(posedge clk) begin
if (rst)
int_ier <= 'b0;
else if (w_hs && waddr == ADDR_IER && WSTRB[0])
int_ier <= WDATA[5:0];
else if (w_hs && waddr == ADDR_IER && WSTRB[0])
int_ier <= WDATA[5:0];
end
// isr_mask
always @(posedge clk) begin
if (rst)
isr_mask <= 1'b0;
else
isr_mask <= isr_toggle;
end
// int_isr[0]
always @(posedge clk) begin
if (rst)
int_isr[0] <= 1'b0;
else if (int_ier[0] & ap_done)
int_isr[0] <= 1'b1;
else if (isr_toggle == 1'b1 && isr_mask == 1'b0)
int_isr[0] <= int_isr[0] ^ WDATA[0]; // toggle on write
end
// int_isr[1]
always @(posedge clk) begin
if (rst)
int_isr[1] <= 1'b0;
else if (int_ier[1] & ap_ready)
int_isr[1] <= 1'b1;
else if (isr_toggle == 1'b1 && isr_mask == 1'b0)
int_isr[1] <= int_isr[1] ^ WDATA[1]; // toggle on write
end
// int_isr[5]
always @(posedge clk) begin
if (rst)
int_isr[5] <= 1'b0;
else if (int_ier[5] & ap_local_deadlock)
int_isr[5] <= 1'b1;
else if (isr_toggle == 1'b1 && isr_mask == 1'b0)
int_isr[5] <= int_isr[5] ^ WDATA[5]; // toggle on write
end
// int_ap_return
always @(posedge clk) begin
if (rst)
int_ap_return <= 0;
else if (ap_done)
int_ap_return <= ap_return;
end
// int_in_r[31:0]
always @(posedge clk) begin
if (rst)
int_in_r[31:0] <= 0;
else if (w_hs && waddr == ADDR_IN_R_DATA_0)
int_in_r[31:0] <= (WDATA[31:0] & wmask) | (int_in_r[31:0] & ~wmask);
end
// int_in_r[63:32]
always @(posedge clk) begin
if (rst)
int_in_r[63:32] <= 0;
else if (w_hs && waddr == ADDR_IN_R_DATA_1)
int_in_r[63:32] <= (WDATA[31:0] & wmask) | (int_in_r[63:32] & ~wmask);
end
// int_out_r[31:0]
always @(posedge clk) begin
if (rst)
int_out_r[31:0] <= 0;
else if (w_hs && waddr == ADDR_OUT_R_DATA_0)
int_out_r[31:0] <= (WDATA[31:0] & wmask) | (int_out_r[31:0] & ~wmask);
end
// int_out_r[63:32]
always @(posedge clk) begin
if (rst)
int_out_r[63:32] <= 0;
else if (w_hs && waddr == ADDR_OUT_R_DATA_1)
int_out_r[63:32] <= (WDATA[31:0] & wmask) | (int_out_r[63:32] & ~wmask);
end
//------------------------Memory logic-------------------
endmodule
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